Metunar has posted some nice videos of the last session at the Chrämerhus in Langenthal:
Illustrator file for some front plates:
Yesterday night we finally got the delay running as it should. Great picture, stable delay:
- Pretty satisfied with picture quality
- Inputs need protection diodes to GND + standard synkie module input protection
- Level shifter seems to work nicely
- delay time is fixed, hardcoded in vhdl right now. Will try to get the rotary encoder working today
With some more clever VHDL coding this could be easily turned into a video looper by making write_enable controllable. Or a synchronized frame freezer. Or a frame synchronizer…
More to come…
Just by deactivating the write command you can easily turn the video delay module into a video looper.
Actually there is no need to seperately refresh the DRAM, because every byte gets read every other second anyway – free auto refresh when the bank is recharged. For loop cycles of at least 3 seconds this seems to work (and with analog video we’re not that picky if sometimes a bit in the stream gets corrupted…) . We had the same loop running for hours without any visual degradation. cool.
While actually programming a CPLD is not possible on Mac, you’re able to compile and simulate: I installed GHDL from here:
ghdl lets you analyze and elaborate a VHDL design + test bench from the command line. Then you can view the simulation as waveforms with gtkwave:
Documentation for ghdl (once installed) is in file:///usr/local/ghdl/doc/ghdl.html
this guide was also useful for me to set things up: http://dcse.die.upm.es/Grupo42/ManualGHDL_v1.1.pdf
see the script ./simulate_Ram_control.sh in the synkie svn repository for how to invoke the simulation from the command line.
I commented out the line that launches gtkwave because you have to launch gtkwave only once, then when you recompile a corrected version you’ll only have to select “Reload Waveform” from the Edit menu. I’m pretty sure this same thing should be possible to do in ModelSim but I just couldn’t figure this shit out.
But cow can actually just double click on the generated .ghw file to see the waveforms.End of Ram Initialisation and first Read/Write cycles
I chose the Altera EPM7128SLC CPLD for my first design for the upcoming synkie delay module because it comes in still a human PLCC84 package. But it’s too small, pin wise but also not enough macrocells to get all the functionality I want for the SDRAM controller.
The problem is that all bigger FPGAS/CPLDS come in much smaller packages. Ball grid array chips cannot be soldered by hand – until I’m able to do DIY reflow soldering – that’s stuff for a next research week – these are out of question…
But even TQFP100 packages are so tiny that I could not even print them on my laser printer without the smd pads touching each other.
Then I found out: vector based programs like Apple’s Preview or Adobe Illustrator do a whole lot of antialiasing when displaying (and printing) the original eps from the EAGLE cam job. The printer actually prints some gray on the edges of the black pads, filling in the space between – and because the pad distance does not fit precisely in the printer’s resolution this creates some sort of moirée pattern. The solution was for me to open the eps file using Photoshop – at 2400dpi without antialiasing (there’s a checkbox for that). This pixel based rendering prints much sharper that the vector based one.Illustrator antialiasing creating gray zones in the gaps.
So the problem was – once again – only in software. With the nice sharp print edging was a breeze (fresh etching solution, all edges of the PCB well filed down to prevent air gaps between transparency and PCB when flashing).
Soldering by hand took a good loupe, some flux, plenity of wick and some patience – but it’s actually quite easy. I even managed to fix some connections I forgot in my layout by soldering wires directly to the pads:sk611 delay – prototype 2
We already did several attempts over the last 3 years to build a video delay module for the Synkie – somehow it’s odd: the whole idea of the Synkie is to get rid of latency when doing live visuals, and then we try hard to bring back some latency into the system…
But a controllable, variable means to delay the signal is sort of the holy grail for me and will open a lot of potential…
To build a delay we have to sample the signal ( at minimum 10 Mhz), store the samples in RAM read them out some time later and convert back to analog. Until now we were not able to build a circuit that creates the necessary control signals in a correct manner . We also tried to use static RAM, because it seemed simpler to interface than dynamic RAM which should be initialized properly and refreshed periodically .
Complex signals on a very tight schedule – we needed some programmable logic to act as a controller for the different parts of the system:
So over the last year I dove into VHDL programming and spent several weeks just trying to install the vendor specific development tools. It’s a strange and bizarre world, with industry heavyweights just trying you to sell you their IP for hard $$$$$ through complex and completely counterintuitive software that weighs in at tens of gigabytes.
I started with Lattice CPLDs. I bought a cheap Laptop to get a clean Windows system, installed their whole suite but then ran into trouble, somehow fried the small development board before I could run my first code on it. Can’t remember the details anymore. Switched to Xilinx – installed their huge ISE Webpack, found out how to simulate and stuff but never managed to program a board. And Microsoft Windows freaks me out.
The last FPGA workshop I attended at dock18 used Altera FPGAs, so I spent another weekend installing all their tools, this time in a virtual machine on my Macbook running Ubuntu Linux 12.3 – now I’m able to do all my editing in BBEdit on the Mac where I’m at home, and just compile and simulate in the shared folder on the linux side of things.
I’m quite happy with this setup, and best of all: It actually works!
Built a first prototype board, downloaded my first VHDL via JTAG and the thing actually displays some delayed out of sync video signal – although in very bad quality over the live signal at the same time. there seems to be some bus contention on the bidirectional data bus between the cold and the sdram.Version 1 of CPLD-driven video delay.
The DS1077 I used to generate a 133 Mhz clock is WAY to jittery, the clock drifts too much: wobbly lines through the picture. tried to use a quartz oscillator but now nothing ticks anymore Anyway the CPLD is too small to fit all the functions I want – will do another prototype with a MAXII…
more to come
Got a broken (and a working) Kramer video processor from Uwe today. It’s a brightness-contrast and color-corrector and I was surprised when I opened it up that its completely analog, so I immediately tried to see what chips they’re using.
In the RGB correction part there’s a MC1496 Modulator/Demodulator, seems quite interesting and it’s still in production and quite cheap at mouser. RGB is converted back to composite through a MC1377P PAL/NTSC Modulator.
Also a TL072 JFET Input Op Amp.
That seems to be all for color correction…
Some 4053 Multiplexers here and there, no surprise. Some AD8056 Dual Op-Amps. Nothing to see here.
The whole circuit seems to be astonishingly simple (well, to be honest, there’s a lot of discrete stuff and filters and trimmable coils, but I was expecting more) – gives me hope to be able someday to build a color correction module….
Accidentally re-read some datasheets today and found out that the MCP662 we quite happily used all over the cv-sections of the synkie does in fact not fit our symmetrical power supply of +-5V. Its max ratings is 6.5V – oops ! We’ll have to replace the all or the will fail some day…
so here some notes on the Op-Amps we are currently using:
- supports high supply voltage of +-18V
- not rail to rail
- only 10MHz gain-bandwidth-product
- 100dB open loop gain
- can offset color phase
- input-bias current of 1µA
DON’T USE: Max 6.5V supply voltage
- nice bandwidth (70MHz), no phase problems
- ATTENTION very high input bias current: typ 5 max 15µA !
- Low open loop gain of 60dB
- Max 12V VDD-VSS